A forward body-biased-low-leakage SRAM cache: device and architecture considerations

This paper presents a forward body-biasing (FBB) scheme for active leakage power reduction in cache memories. We utilize super high V/sub T/ (threshold voltage) devices to suppress the leakage power in unselected portions of a cache while fast operation is achieved by dynamically forward body-biasing the selected SRAM cells. In order to generate a super high V/sub T/ device, the 2D halo doping profile was optimized by considering different nanometer regime leakage mechanisms. The transition latency and energy overhead associated with FBB could be minimized by (i) waking up the SRAM cells ahead of the access and (ii) exploiting the cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bitline delay compared to a previous state-of-the-art low-leakage SRAM technique.