Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance

Carbon Nanotube Field-Effect Transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10 nm transistor era. This paper presents a novel circuit-compatible modeling of CNFETs in their ultimate performance limit. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE.