High density and high performance ECL: some design tips

Recent developments in ECL (emitter-coupled logic) circuit technology have led to a new generation of high-density and higher-performance gate arrays. The choice of an ECL ASIC (application-specific integrated circuit) technology is discussed with regard to the use of proven versus new technology, ASIC benchmarks, and second sourcing. Design issues considered are the optimization of density and performance, power limits, estimated versus actual interconnect delays, pulse shrinkage and clocking, packaging, and cooling.<
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