Design and FPGA implementation of high-speed square-root-raised-cosine FIR filters

A series of square-root-raised-cosine (SRRC) FIR filter with CSD coefficients were designed according to the local search algorithm based upon minimax error criteria. The simulation results of a baseband system show that two 13-tap SRRC FIR filters with a roll-off factor 0.6 only introduced about 6% peak distortion in the eye pattern. A bit-level pipeline architecture was used to realize the high sampling rate FIR filter. An additional tap with fixed input of 10 was added to the final stage of the filter to avoid carry ripple. Consequently, the critical path consists of only a single one-bit full adder and a pipeline register. The filter was implemented in an altera's FPGA: EP20K60EFC144-1 and the timing analyses results show that the sampling rate could be over 200 MHz.