A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic

In this work, a 32-bit tree-structured carry lookahead adder (CLA) is proposed by using the modified all-N-transistor (ANT) design. The 32-bit CLA not only possesses few transistor count, but also occupies a small area size. Moreover, the post-layout simulation results given by TimeMill show that the clock used in this 32-bit CLA can run up to 1.25 GHz at 3.3-V power supply. The output of the proposed CLA will be ready after 3.5 cycles. The proposed circuit is also easy to be expanded for long data additions. A physical chip is fabricated to verify the proposed circuit on silicon.