Linear filtering using reconfigurable computing

Summary form only given. We present the mapping and performance analysis of a linear filtering algorithm on one of the reconfigurable computing (RC) prototypes, MorphoSys (M1) system. Mapping of a linear filtering algorithm, namely convolving a filter kernel across an image, onto this hardware is proposed. A performance analysis study is examined to evaluate the efficiency of the algorithm execution on the M1 RC system. For instance, an algorithm to convolve 8/spl times/8 image pixels with 3/spl times/3 filter kernel on the M1 8/spl times/8 RC array was run. Numerical examples were simulated to validate our results using the MorphoSys mULATE program, which simulates MorphoSys operations. Results showed that MorphoSys yielded a superior performance compared to the TMS320C40 DSP microprocessor.