Behavioral modeling to circuit design steps of a 3-V digital audio sigma-delta modulator in 0.35/spl mu/m-CMOS

In this paper the design and simulation procedure of a digital audio sigma-delta modulator is discussed. The circuit non-idealities of the modulator such as KT/C noise and OTA performance parameters are modeled behaviorally using SIMULINK/sup /spl reg//. The required circuit specifications are extracted from the behavioral simulation results. In order to get 16-bits of resolution for a 25-KHz signal bandwidth, an optimum choice was a second order modulator with an over-sampling ratio of 256 and sampling frequency of 12.8 MHz. To test the design procedure validity the modulator has been designed with fully differential switched capacitor integrators in a 0.35-/spl mu/m double poly, four metal CMOS process. Circuit simulations indicated 90 dB of peak SNDR from a single 3 V supply and 4.5-mW power consumption.