A new CMOS gate-the balanced gate-for detecting physical failures

An approach to design-for-testability of CMOS logic circuits is presented. The method is based on design with a new family of gates, called balanced gates. These gates have an extra logic level that is used for testing. In the test mode, all the inputs to a gate are at 2.5 V, and if there are no faults the output would be at 2.5 V (gate is balanced). Circuits made with this family of gates require one test vector (2.5 V for each input) to achieve an acceptable level of fault detection. Simulation results indicate that circuits made from balanced gates are easily testable.<
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