Ultra low Cout/spl times/Ron photo-relay using depleted drift layer in thin film SOI

In this paper, we propose a new concept of a MOSFET switch for small-outline photo-relays. By applying the concept of depleted drift layer to the thin film SOI MOSFET, the developed photo-relay switch has achieved the lowest Cout/spl times/Ron (product of output capacitance and on-state resistance) of 1.87 pF/spl Omega/ for 26.5V device and 4 pF/spl Omega/ for 43V device, respectively. These values are the lowest ever reported. The packaged photo-relays achieved low off-state leakage current and low output pin capacitance, being sufficient to be used 2-3 MHz frequency range measuring instrument.