Signal integrity analysis of high-speed, high-pin-count digital packages

A transmission-line model of package traces in conjunction with a lattice diagram technique is used to study the signal integrity problem in digital systems using high-speed, high-pin-count packages. Formulae which predict the signal degradations, including overshoot/undershoot and edge-rate degradation, are presented for two different high-speed digital system interconnect schemes (parallel termination and series termination) at different locations of the interconnect (output, input, package-board junction, etc.) Among different degradations at various places on the interconnect, the one of most concern to system designers is the reflection noise in multiple fanouts or bidirectional buffers. An experimental procedure was developed to verify this problem and to quantitatively measure the magnitude of the reflection noise. An experimental 288-PGA (pin-grid-array) package which may represent the current package technology was chosen for this experiment. The results clearly indicate that package parasitics can substantially affect the signal integrity of current high-speed digital systems. According to the present study, it is not possible to choose a single package impedance Z/sub p/ which can give optimized signal response everywhere along the interconnect. It may be a design tradeoff to choose a particular package impedance for a specific system. However, the study also indicates that choosing a package impedance is far less important that minimizing the package delay.<
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