Gigahertz waveform sampling and digitization circuit design and implementation

A series of multichannel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel 10-bit digitization have been designed, tested, and fabricated in large quantities. The current CMOS circuit uses four arrays of 128 fast switched capacitors per channel to record four parallel analog transient inputs. High-speed sample clock generation is provided by an analogically adjustable asynchronous active delay line that uses look-ahead to generate 128 multi-GHz four-way interleaved clocks without the need for external high-speed clocking. After transient capture, each channel is fed into 128 parallel 10-bit analog to digital converters for fast, channel-parallel digitization, followed by digital readout. The fast triggering and waveform capture, channel-parallel digitization and convenient word-parallel digital readout results in a responsive and low dead-time system. Acquisition sample rates range from /spl sim/50 kHz to /spl sim/3 GHz. Analog input bandwidth was measured to be /spl sim/350 MHz. Temporal noise is typically equivalent to /spl sim/1 mV root mean square (rms) for a signal-to-noise ratio of /spl sim/2500:1 rms. Fixed-pattern spatial noise, after on-chip digitization, is equivalent to /spl sim/5 mV rms. Current design directions are intended improve on this technology with sample rates in excess of 10 GHz and an analog bandwidth exceeding 1 GHz.