Power and ground plane inductance (for single-chip package)

The inductance of the power and ground planes and associated vias is investigated for a high-performance single-chip package. The current distribution in the planes is determined using a novel vector potential. The magnetic intensity in all spatial coordinates due to these currents is determined by the Biot-Savart law. The inductance is proportional to the stored magnetic energy. Special methods for finding the inductance of vias are established. The total inductance is determined. The voltage and ground-plane inductance accounts for less than one quarter of the total, and tab leads and vias are the seat of most of the inductance. To reduce that inductance, shorter, fatter leads can be used, and leads carrying currents in opposite directions should be placed close together to provide as much mutual inductance as possible to cancel self-inductance.<
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