A 90 nm 1 GHz 22 mW 16/spl times/16-bit 2's complement multiplier for wireless baseband

This paper describes a static 16/spl times/16-bit 2's complement wireless baseband multiplier testchip in 1.2 V, 90 nm dual-Vt CMOS technology. One-hot Booth encoding, sum/delay difference optimized 3:2 compressor tree, and signal-profile optimized final adder schemes are employed to achieve 1 GHz, 22 mW operation at 1.2 V, scalable to 500 MHz, 3 mW at 0.8 V.