Study of substrate noise and techniques for minimization

This paper presents a study of substrate noise effects on analog circuits and a technique for minimizing substrate noise. Measured data of a 0.25 /spl mu/m CMOS test chip reveals that substrate noise couples through circuit asymmetries and nonlinearity, degrading analog circuit performance. An active substrate noise shaping circuit implemented on the same test chip demonstrates over 10 dB improvement in SNDR in the 0-20 kHz band of a delta-sigma modulator for substrate noise generated by an inverter array.