Stress relaxation in dual-damascene Cu interconnects to suppress stress-induced voiding

Stress-induced voiding (SIV) was investigated for 130 nm node dual-damascene Cu interconnects. Three SIV failure modes were revealed by TEM analyses. Cumulative failure was investigated at various metal widths, via shape and via position on a metal line at 150/spl deg/C at which the maximum failure rate was observed. Stress-induced failure at narrow Cu line was also observed, which is associated with tensile stress in Cu calculated by 3D finite element method (FEM) stress analysis. Stress relaxation by dielectric structure and quenching process were demonstrated based on stress simulation, thus the resulting SIV failure was suppressed.