Interconnect and noise immunity design for the Pentium/spl reg/ 4 processor

This paper describes the key challenges, design methods, CAD and learnings in the area of interconnect and noise immunity design for the Intel Pentium/spl reg/ 4 processor. This high frequency (currently at 3 GHz with 6 GHz execution core) design required aggressive domino, pulsed and other novel high speed circuit families that are very noise sensitive. Controlling interconnect delay, capacitive and inductive coupling is of paramount importance at such high frequencies and edge rates, made more difficult by die cost pressures of a high volume chip. We first describe our wire/repeater design methods and silicon results. We then describe a proprietary noise simulator (NoisePad) and our noise robust cell library, both of which were critical to noise robustness. Finally, our test chip results and use of a distributed power grid to manage inductance is described.