30 nm MOSFET development based on processes for nanotechnology

30 nm nMOSFETs were fabricated on bulk-Si by processes for nanotechnology: the sidewall patterning technique, the RTO process and As/sub 2//sup +/ low energy implantation. With the aid of the sidewall patterning technique, very fine line patterns could be made accurately, uniformly and reproducibly all over the wafer. The RTO process made it possible to realize very thin oxide uniformly all over the wafer. As/sub 2//sup +/ implantation realized 12 nm shallow n/sup +/-p junctions. Based on these processes, 30 nm nMOSFETs were realized and their electrical characteristics were analyzed. They were 30 nm in channel length, 9 ? in channel width and 1 nm in gate oxide thickness. Their threshold voltage was 230 mV. They had drive current of 360 ?/? and maximum intrinsic transconductance of 700 mS/mm at 1.0 V. Also, DIBL was 250 mV/V and subthreshold slope was 110 mV/dec. The 30 nm nMOSFET showed normal transistor operations in 30 nm regime with the planar structure on bulk Si.