Design and implementation of high and low modulo (2/sup 16/ + 1) multiplier used in IDEA algorithm on FPGA

In this paper the design and the implementation of high and low modulo (2/sup 16/+1) multiplier used in the international data encryption algorithm (IDEA) is presented. The used mathematical formula for each multiplier is provided. The comparison between the high and the low modulo multiplier is discussed and the comparison is performed according to the following: the multiplier location in IDEA structure, the process whether encryption or decryption, the used inputs and keys, the number of gates and the maximum speed. Exploring the differences between them will result in the following: the correct encryption/decryption process, the complete definition of IDEA, increased number of gates in the design of high modulo multiplier to correct the zero input state problem, the ability to customize the IDEA and to increase the operating speed of the target IDEA chip. The two modulo multipliers are implemented on Xilinx FPGA Spartan II family and the target chip is XC2S100-5PQ208C.