Design optimization methodology for deep-submicrometer CMOS device at low-temperature operation

The design optimization for 0.3- mu m channel CMOS technology at liquid-nitrogen temperature (77 K) is described. The tradeoff between circuit performance and reliability for deep-submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator, which selects power-supply voltage and process/device parameters for low-temperature operation, has been developed. Based upon the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. The optimized design has been demonstrated on a 0.3- mu m CMOS device, by utilizing electron beam (EB) lithography. Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K.<
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