Dynamic asynchronous logic for high-speed CMOS systems

As transistor switching speed improves, synchronizing a global clock increasingly degrades system performance. Therefore, self-timed asynchronous logic becomes potentially faster than synchronous logic. To do so, however, it must exploit the techniques used in fast synchronous designs, including redundant logic, inverting logic, transistor size optimization, dynamic logic, and phase alignment. Most techniques can be applied equally well to asynchronous logic-indeed phase alignment is easier-but combining dynamic and asynchronous logic is more difficult. Minimum refresh intervals together with race- and hazard-free operation must be guaranteed. An initial chip implementation that combines dynamic and asynchronous logic running at 500 MHz in 2- mu m CMOS is described. With the addition of transistor size optimization, simulations show the same circuit running in the same technology at 800 MHz.<
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