A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2- mu m CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW.<
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