Local oscillator generation scheme in 0.18 /spl mu/m CMOS for low-IF and direct conversion architectures

A fully-integrated, ratio-based local oscillator (LO) generation scheme using regenerative division is described. Using 0.18 /spl mu/m CMOS technology, the core LO system consumes 27 mW from a 1.8 V supply. The entire chip is fully integrated, including on-chip spiral inductors; harmonic rejection mixers are also employed to suppress unwanted mixing products to better than -36 dBc. Across a bandwidth of 150 MHz, centered at 1.63 GHz, a quadrature phase error of less than 2 and a maximum image suppression of 36 dB is achieved. Using a 4/3 multiplication factor to generate the local oscillator, LO-RF interactions are reduced and an LO-RF leakage of -86 dBm has been measured at the mixer input. This system can be utilized in low-IF or direct conversion architectures.