Power efficiency of application-dependent self-configuring pipeline depth in DSP microprocessors

We illustrate the results of a simulation-based analysis of "self-configuring" pipeline depth in DSP computations, focusing on the effects on power efficiency. We use three different metrics for power efficiency: mips/watts, mips/sup 2//watts, and watts under an absolute performance constraint. Our results, based on a set of commercial DSP benchmarks, show that an application-dependent self-configuring pipeline depth significantly affects power efficiency.