Synchronous programmable divider design for PLL using 0.18 /spl mu/m CMOS technology

In the wireless communication market, trends are moving towards smaller size, fewer parts, longer lifetime and higher frequency operation. These trends imply that wireless communications circuits must incorporate higher integration and that their design and IC technology must be optimized for low power and high frequency system. One innovative method to increase the frequency of programmable divider is discussed. The new method not only increases the frequency of operation but also decreases circuit complexity and power dissipation. This new design use synchronous counters instead of asynchronous counters. The digital gates are optimized for minimum propagation delay and loading effect using progressive sizing of the transistors. This is better configuration in every aspect in terms of frequency, power dissipation and chip area.