A macroscopic behavior model for self-timed pipeline systems

We present a novel macroscopic behavior model for self-timed pipeline (STP). STP is a promising architecture for system-on-chip (SoC) design, because STP eases the timing problems and abnegates the control dependencies among building components to prevent the parallelism and integrity. In earlier evaluation processes, a cycle-based simulation takes too long and too much memory to survey the wandering behavior of STP. From the theoretical point of view, throughput of a STP system depends on the occupied rate. This leads to the production of our new model, which only manages the position and velocity of packets. Our behavior model omits the precise status of each stage in a pipeline to save these simulation costs. Simulators based on the existing naive model and on our model show equivalent results, while the latter is about 1.5 to 5 times faster than the former. Both models are applied to a ring style STP which is used in real processor's hardware implementation. Also, a 4 multiprocessor system connected by STP network executing an image processing was successfully simulated.