Efficient core designs based on parameterized macrocells with accurate delay models

A new design methodology targeted for core-based designs using parameterized macrocells (PMCs) is proposed. This methodology provides the flexibility for instance-based cores to be easily customized for application specifics. By using few scaling parameters to characterize a PMC, a macrocell can be instantiated in virtually any size depending on the required performance. Moreover, new macro delay and peak current models which are function of the PMC scaling parameters are proposed. These models enable accurate delay and peak current predictions at the subsystem/core level. The macro delay model is suitable for use in a delay optimizer to determine the optimum scaling parameters of individual PMC's in a core. The peak current model is useful for computing the peak current drawn by a PMC which allows efficient power rails sizing in order to address power grid reliability issues. A PMC library has been developed using the proposed methodology and used to design cores for communications applications. To demonstrate the effectiveness of the proposed methodology, a subsystem used in a channel decoder application was synthesized using this library where the individual PMC's were optimized for delay. The resulting custom-quality layout has an area of 50 /spl times/ 100 /spl mu/m/sup 2/ and a delay of 1.6 ns in 0.18 /spl mu/m, 1.8 V CMOS technology.