Low-power CMOS circuit techniques for motion estimators

To drastically reduce the active power (P/sub AT/) and the stand-by power (P/sub ST/) of the CMOS motion estimator (ME), several power reduction techniques were developed. They were circuit architectures that were able to reduce supply voltages (V/sub D/) and numbers of logic gates, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.13-/spl mu/m CMOS accumulation-type ME (AME) LSI has been developed by using those techniques. At clock frequency of 220 MHz and V/sub D/ of 0.73 V, P/sub AT/ was reduced to 51.2 /spl mu/W, which was 16.3% that of a conventional AME. P/sub ST/ was 9.92 nW, which was 9.58% that of the conventional AME.