A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders

In this paper a systematic methodology for designing parallel-prefix modulo 2/sup n/ - 1 adders, for every n, is introduced. The resulting modulo 2/sup n/ - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims at the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area /spl times/ time complexity reduction of up to 46% when compared to previously reported designs.