Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

A simple yet accurate closed-form delay expression for inverter driven on-chip interconnects with arbitrary receive-end termination is presented. The solution can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing schemes. The model is extended to consider fast input slope and input-to-output capacitance effects of a CMOS inverter. A test chip fabricated in AMI 1.6 /spl mu/m is used to experimentally verify the proposed model. Further analysis shows that the model can be used for sub-micrometer process to accurately estimate delay and bandwidth performance of long onchip interconnects.