Implementation of a parallel turbo decoder with dividable interleaver

In this paper, VLSI architecture for an efficient turbo decoder with parallel architecture has been studied to achieve high-throughput. For 100% PE utilization, a dividable interleaving method is proposed, which not only solves the memory conflict problem in extrinsic information memory, but also reduces the required memory for interleaver. We mapped the proposing parallel turbo decoder with 4 SISO's and a dividable S-random interleaver with 0.35 /spl mu/m CMOS technology, which occupies 21.6 mm/sup 2/, supports up to 41.8 Mb/s decoding rate.