Cost-oriented design of a 14-bit current steering DAC macrocell

This paper presents the design concept and implementation of a 14-bit current steering DAC macrocell for a SoC in 0.13 /spl mu/m CMOS. The design approach minimizes total fabrication cost of the SoC. The paper demonstrates that using this approach smaller and economically efficient DACs will result without a loss to specified design requirements.