Design techniques for a fully differential low voltage low-power flash analog to-digital converter

A CMOS 8-bit, 33.3MS/s flash ADC with /spl plusmn/1.5V power supply is developed through the use of a low-power high-speed CMOS fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than /spl plusmn/0.3LSB. Signal-to-(noise and distortion) ratio is 46.2dB at a sampling rate of 33.3MS/s and input frequency of 4MHz. The power dissipation is 106mW at 33.3MS/s with /spl plusmn/1.5V power supply.