New very compact CMOS continuous-time low-voltage analog rank-order filter architecture

A new and very simple CMOS continuous-time analog rank-order filter architecture is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transistors per input. It is based on a multiple input differential structure. Rank is easily programmable with the tail current source for all rank order values from the max to the min case. The circuit has low voltage and power consumption requirements. Output buffered versions and techniques for reduction of corner errors are discussed. Experimental results are presented that verify the functionality and accuracy of the proposed circuit. Simulations show potential for operation in the 100 MHz range in 0.18 /spl mu/m CMOS technology.