Damage-free SiO/sub 2//SiN/sub x/ side-wall gate process and its application to 40 nm InGaAs/InAlAs HEMT's with 65% InGaAs channel

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual SiO/sub 2/ and SiN/sub x/ dielectric layers and the proper selection of the etching gas, the final gate length (L/sub g/) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40 GHz, extrapolated f/sub T/ and f/sub max/ as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the 100 nm range.