R-/spl beta/R ladder networks for the design of high-accuracy static analog memories

In this paper, we show that the topology of successive approximation analog-to-digital converters can be used for the realization of a static analog memory (SAM), that is a circuit capable of indefinitely maintaining at its output a voltage close to the one presented at its input for a limited time. After demonstrating that the accuracy which can be obtained in the storage process is limited by the maximum positive value of the differential nonlinearity of the digital-to-analog converter (DAC) used as part of the circuit, we demonstrate that by means of a proper choice of the ratio of the resistances of the ladder network of the DAC, very high accuracy can be obtained even by employing poor tolerance resistors, without the need for any trimming or calibration step. This fact might be advantageously exploited for the design of integrated multichannel SAMs which, employed in connection with a single high-accuracy DAC, could allow the realization of multiple output, high-accuracy, programmable voltage or current sources.