Micropower low-voltage analog filter in a digital CMOS process

Techniques for implementing micropower analog filters using digital CMOS process technology are described. PMOS devices operating in accumulation are used for the integration capacitors, and the voltage swing across them is limited by employing current-mode operation using the log domain approach. The latter is implemented using enhanced lateral bipolar transistors. A second-order low-pass filter with a cutoff frequency of 22 kHz, fabricated in a 0.25-μm digital CMOS technology, consumes 4.1 μW from a 1.5-V supply and has an rms output noise of 0.25 nA. The filter's signal-to-noise ratio at 1% total harmonic distortion (THD) is 56 dB and its maximum S/(N+THD) is 45 dB. The chip occupies 0.085 mm
²
.