A method to comprehend the impact of interconnect coupling effects on gate oxide reliability

A method to quantify the interconnect coupling effects on gate oxide reliability is developed. Post-layout noise waveforms at each gate node are obtained by using TCAD noise simulation tools. These waveforms are used to determine an average time to fail (TTF), which is eventually used in gate oxide failure probability calculations. Additionally, the TTF is translated to a DC equivalent voltage (DCEV) for quantification of the coupling impact in terms of voltage.