Investigation of wafer level burn-in to SoC memory: 1TRAM

This paper investigates the effect of Wafer Level Burn-In (WLBI) on retention time of 1TRAMs by using a simple and practical gate oxide stress method. We find that the WLBI stress time does not influence the degradation of retention time when we continue to increase the stress time beyond 40 s in WLBI. We try to clarify retention time degradation in long term WLBI by experiments. A 1TRAM memory is utilized to ascertain whether the WLBI mode is successfully implemented or not. Moreover, the WLBI method is compared with traditional Package Level Burn-In (PLBI). By using WLBI, gate oxide defects in 1TRAM cell arrays can be screened in CP (Chip Probing) testing and the method can be applied to other memory products.