Transmit and receive digital filters subject to hardware cost constraints

A method for the design of field programmable gate array (FPGA) based bit-serial Finite duration impulse response (FIR) transmit and receive digital filters is presented. Transmit and receive digital filters can be designed with near zero inter-symbol interference (ISI) and a specified normalized minimum stopband attenuation while using a specified number of logic elements (LEs). A tradeoff between the ISI and the hardware cost (the number of required LEs) is explored. It is shown that it is possible to obtain low cost transmit and receive digital filters at the expense of higher ISI.