Threshold-voltage balance for minimum supply operation [LV CMOS chips]

The difference between the threshold voltages V/sub t/ of pMOS and nMOS transistors is a critical issue in the low-voltage operation of CMOS circuits. The pMOS/nMOS V/sub t/ balancing profit is analyzed in terms of subthreshold leakage current and the performance of CMOS LSIs and the minimum supply voltage of logic circuits. Matching the pMOS/nMOS V/sub t/ improves LSI performance and reduces the lowest supply voltage by 0.15 V. We propose a new concept of body bias management that uses forward biasing, fluctuation compensating, and V/sub t/ matching technologies to resolve the issue.