IBM's 50 million gate ASICs

There is no slowdown in the complexity increase for ASIC and SoC designs. As we write this paper in August, 2002, 40 M gate ASICs are nearing tape-out, and 50 M gate designs are likely to start before this conference takes place. This paper describes the current tool and methodology development efforts focused on enabling ASIC and SoC designs of these sizes and complexity, centered around the reduction of design turn-around-time, improvement of the quality of results and the modeling and optimization of deep sub-micron electrical effects.