Minimum-size effects in asymmetric tilt-angle-implanted LDD-WN/sub x/-GaAs MESFET's

Asymmetric tilt-angle-implanted lightly doped drain (LDD)-WN/sub x/-GaAs MESFETs with an optimized transconductance performance are discussed. A tilt-angle implantation is used to reduce the parasitic source resistance below the gate sidewall without increasing short- and narrow-channel effects. This leads to a transconductance increase of nearly 25% for submicrometer FETs while the gate-source capacitance increase is almost negligible. The influence of the implantation angle on the threshold voltage transconductance, and Schottky-barrier characteristics is reported.<
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