Real-time packet editing using reconfigurable hardware for active networking

An active network node architecture, called Active Packet Editing (APE), is proposed. The main concept of APE is to accelerate functions essential to active network operation, such as packet classification and NAT (Network Address Translation). The twofold architecture of APE combines a software active packet processor with a high-speed hardware packet editor. Based on preset rules (pattern, action), the packet editor classifies and modifies packets passing through the node. Upon the receipt of active packets, the software active packet processor dynamically configures the packet editor. This paper focuses on introducing the high-speed packet editing mechanism which utilizes FPGAs (Field Programmable Gate Arrays) and CAMs (Content Addressable Memories). A prototype network node based on the architecture performs Gigabit-class throughput with packet editing.