A class of power efficient VLSI architectures for high speed turbo-decoding

Turbo codes have become an attractive forward error correction scheme for broadband communications, providing near optimal coding gain. However, the limited throughput, the large latency and the significant power consumption of their current implementations make them hardly suitable for future broadband communication systems (up to 1 Gbit/s). We have developed an innovative turbo-decoding architecture that overcomes these major drawbacks. We increased drastically the throughput and decreased the latency by introducing a high level of parallelism. We reduced significantly the power consumption by optimizing the memory architecture and organization. This paper presents the proposed architecture as a generic, scalable and parametrizable entity. Design trade-offs regarding decoding performance, energy consumption and silicon area are extensively explored and summarized in cost versus throughput curves, enabling an optimal tuning of the proposed architecture to future applications. A net coding gain of 8 dB, a throughput of 500 Mbit/s and a latency of 10 /spl mu/s are achievable with a typical power budget of 1 W and a die size of 20 mm/sup 2/ in 0.18 /spl mu/m CMOS technology. At lower throughput (around 10 Mb/s), the power can be reduced to 10 mW and the area to 5 mm/sup 2/.