A parallel algorithm for power estimation at gate level

In this paper we present an analytical method for estimating switching probability and power consumption of combinational circuits at the gate level. Considering the signal correlation and multiple-bit input switching, we propose an efficient scheme to estimate switching probability and dynamic power consumption of combinational CMOS circuits at the gate level accurately. Additionally, our algorithm has potential not to propagate the estimated values through the circuit and thus can be run in parallel machines for very large circuits.