An adaptive low power texture mapping architecture

The texture mapping stage is one of the most power consuming stages of the modern 3D graphics pipeline, due to its extensive computation and off-chip memory accesses. In this work, an adaptive texture mapping architecture is proposed, which achieves low-power by facilitating two types of data pattern sensitive transformations that reduce complexity of the computations. These transformations have been shown to achieve power savings in the range of 30% to 53% from the interpolation unit, the main power consumer of the texture mapping system. Systems with ability to obtain low power by tuning their supply voltages to the throughput requirements are gaining increasing prominence. Two more techniques namely adaptive datapath partitioning and dynamic voltage scaling based on the algorithm selected for texture mapping have been proposed for achieving significant power savings in these scenarios. These techniques can facilitate up to 79.5% and 59% power savings from the interpolation unit and the entire texture mapping system respectively.