A 0.58-1 Gb/s CMOS data recovery circuit using a synchronous digital phase aligner

A data recovery circuit using a newly proposed synchronous digital phase aligner is realized for multi-link applications. The proposed circuit is implemented with 0.35 /spl mu/m CMOS process technology. The experimental results show that the proposed circuit successfully recovers incoming 0.58-1 Gb/s of 2/sup 31/-1 pseudo random bit sequence with less than 10/sup -14/ of bit error rate.