Power comparison of throughput optimized IC busses

Globally asynchronous bus designs are considered theoretically attractive for saving power. In this work we design and compare asynchronous and synchronous busses in 0.13um and 0.10um technologies based on bus-wires that are optimized for throughput per unit channel area. At high frequency the synchronous data bus wire power exceeds that for the asynchronous design due to the higher latch-repeater power. In contrast, the asynchronous bus control power is greater than the local synchronous clock power until a sufficient number of bus lines share the control line. Based on a reasonable switching activity factor for the lines (e.g. /spl sim/15%), however, a shared control line can be considered as switching continuously for 32 bits or more, while the bus is being utilized. The power benefits of asynchronous, therefore, are questionable for applications such as globally asynchronous locally synchronous (GALS) methodologies. Moreover, the distinction between asynchronous and synchronous is marginal if we further consider a synchronous control line with a local pulse-generation circuit to drive half-latch repeaters in the data bus path.