Optimization of 1.8V I/O circuits for performance, reliability at the 100 nm technology node

We describe the methodology and challenges in designing robust receiver and driver buffers in a state-of-the-art sub-100 nm CMOS technology. Issues addressed are the gate voltage limitations due to very thin gate oxides, channel hot carriers, process variability and design margins. The bi-directional buffer is 90 /spl mu/m/spl times/114 /spl mu/m in size and has a maximum speed of 150 MHz with a 50 ohm termination.