A fast macro based compilation methodology for partially reconfigurable FPGA designs

In this paper, we propose a methodology for automated mapping of a design onto a partially reconfigurable device. We generate partial bitstream files from behavioral description of the task, that are used to reconfigure the device dynamically. The novelty of this research lies in the application of a macro based synthesis approach that allows elimination of both logic synthesis and technology mapping phases from the synthesis flow. Our methodology provides a significant reduction in compilation time compared to commercial tools.